In semiconductor device fabrication oscillators are known in numerous applications, such as clock references, frequency synthesis and many others, to provide timing signal for handling information. Transistor-based oscillators have been built into semiconductor wafers or chips as test structures. The behavior of the oscillators depends on the characteristics of the transistors and interconnects from which they are made. Since the oscillators are made using the same transistor, metal, and insulator layers as other devices in the chip, such test structures can provide information about the performance of the chip at-speed.
One type of oscillator is based on inverters connected together in a ring. An inverter produces an output voltage opposite to its input. For example, an inverter may invert a low voltage (e.g. logical zero) to high voltage (e.g. logical 1), providing a full swing so that amplification is not necessary. As illustrated on FIG. 1A, a single inverter may consist of two transistors 110 and 120. The gates 114 and 124 of those transistors are tied together at an input 102, and drains 116 and 126 are tied together at an output 104. The source 112 is connected to a source voltage 118 and source 122 is connected to the ground 128. When input 102 is a logical “1”, transistor 110 becomes conductive and transistor 120 becomes non-conductive. Thus a logical “0” is transmitted to output 104. If a logical “0” is applied to input 102 transistor 120 becomes transparent and transistor 110 becomes opaque thus a logical “1” is transmitted to output 104.
A ring oscillator may be constructed from odd number of inverters connected in a ring. A typical three-inverter or three-gate ring oscillator 101 is shown on FIG. 1B. Inverters 130, 140, 150 are connected in a ring so that outputs 134, 144 and 154 of each inverter are coupled with the inputs 142, 152 and 132 of the next inverter in a ring. Three-inverter oscillators can be made to oscillate at frequencies of about 2.3 GHz. A three-gate ring oscillator has three phases because each of the three outputs transition between states at different times due to the delay between the changes of a given input-output. If finer separation is required, more stages may be added, e.g., as in a five or seven gate ring oscillator. Adding more stages also makes the ring oscillator circuit oscillate at a lower frequency.
Product sort ring oscillator (PSRO) structures and other active at-speed device test structures including delay lines, memory cells and the like are used to assess transistor and interconnect performance as a routine part of wafer test, typically at the Metal 1 stage of manufacturing. Test structures are built in the scribe line and may also be embedded within the active area of the device to reveal cross chip transistor performance variation. The PSRO oscillation frequency is indicative of device switching speed (also known as gate delay or propagation delay). Furthermore, the oscillator bandwidth may provide an indication of characteristics such as capacitance, resistance, etc. of the devices and interconnect structures. Therefore, PSRO oscillation frequency and bandwidth are highly indicative of end of line device performance. The use of PRSO's enables early and more definitive yield prediction, process feedback and feed-forward, including refined yield/performance tradeoffs to be made in subsequent process steps to optimize gross margin per wafer. This information complements less convolved parametric information such as linewidth and film thickness.
Typically the test structures are powered by external power sources via mechanical contact probes to test pads on the wafer. Metal traces on the wafer connect from the test pad to the PSRO. Signals from the test structure are also accessed by precision contact probes. Typically mechanical probes access several different regions of a wafer at a time, making contact to individual test structures and measuring them in parallel. This process requires accurate navigation of the probes to space-consuming contact pads, jeopardizes yield due to probe contact and defect generation close to the product devices, and requires complex and expensive test equipment as well as precision probes. Furthermore, it is generally a slow process since multiple sites on the wafer must be measured serially.
Recently it has been proposed to power-up devices and to enable probing of test structures in a non-contact manner. In one proposed prior art powering scheme, PSRO's are powered by illuminating embedded photocells on the wafer, which are connected to the PSRO. Power for the PSRO and DC or AC test signals are generated by on-chip photodiodes energized by an external light sources or thermal sources. Signals from the test structure can be measured using a variety of non-contact techniques, including RF emission, Kelvin probe, optical probing etc. The advantage of this is that the test structures can be probed without damage at multiple stages during the fabrication process. Unfortunately, the embedded photocells increase the footprint of the test structures. Furthermore, the need to tightly define the spatial extent of the illuminating beam means that the measurement method requires high spatial precision and sophisticated optics, and thus does not serve the goal of measuring multiple sites simultaneously across an entire wafer.
What would be desirable is a method by which all test structures on an entire wafer could be simultaneously powered up and analyzed at various stages during device processing, without need for local contact to the devices, large test pattern footprint, navigational precision, expensive test equipment, precision optics or precision alignment of probes.
It is within this context that embodiments of the present invention arise.